1. Field of the Invention
The present invention relates to user-programmable integrated circuits. More particularly, the present invention relates to a substrate architecture for face-to-face bonding to multiple daughter chips.
2. The Prior Art
As process geometries scale, the portion of the area of digital-logic function integrated circuits such as field-programmable-gate-array (FPGA) integrated circuits and mixed digital and analog function integrated circuits that must be devoted to input/output (I/O) represents an increasing percentage of the die area relative to logic gates. A secondary cost issue is that often customers may need a significant amount of I/O and not many gates. Presently, such customers end up paying for un-needed gates in order to obtain needed I/O. The reverse is true as well. This represents an opportunity to deliver a more cost-effective product to customers.
Another problem is that some manufacturers envision creating a number of system-on-a-chip (SOC) integrated circuits and derivatives that employ FPGA and other programmable logic technology. These derivatives will have varying quantities and functions of analog peripherals depending on application. Many variations of analog peripherals are envisioned. In addition, the number of FPGA gates needed for each set of peripherals will be customer dependent, again creating a situation where the customer is paying for un-needed gates.
The industry has not come up with a good solution for the I/O problem to date. The current trend is to make several I/O rings and offer variations of products in different combinations with different gate counts. Another solution is to use so-called I/O immersion where I/Os can be programmed anywhere in the FPGA fabric, thereby decoupling the number of I/O circuits from the number of logic gates. This solution however requires flip-chip packaging. Flip-chip packaging is the art of bonding pads distributed anywhere on the face of an IC directly to a package without use of wires. Flip-chip packaging, presently and in the reasonably-forseeable future, will still add enough cost to the product to offset any cost savings realized from the solution.
The industry in general is looking at a number of so-called 3-D packaging variations. None of these variations are employing 3D packaging to solve the above-described I/O problem.